The release of the AMD EPYC Rome 7-nm server processors is scheduled for half of this year, but for now the samples of these chips have been tested in the chip makers' laboratories and its partners.
For example, a 32 core EPYC Rome processor with the identifier ZS1711E3VIVG5_24 / 17_N was displayed in the SiSoftware Sandra database. This engineering instance was operating at a base frequency of 1.7 GHz with the possibility of a dynamic acceleration up to 2.4 GHz, which is slightly lower than that of similar EPYC 7000 series chips.
Two months ago, the second-generation 64-core AMD EPYC managed to fire up SiSoftware's Sandra database as part of the Dell PowerEdge R7515 server. It is curious that the hero of today's note was installed on the younger PowerEdge R6515 server. As pointed out by Dell previously, the company will increase the supply of AMD-based servers by a factor of three compared to the recent period.
If we consider in detail the identification of the ZS1711E3VIVG5_24 / 17N chip, so besides the 1.7 / 2.4 GHz frequency, we can conclude that there are 16 MB of second level cache memory and 128 MB of L3 cache. The "Z" prefix refers to the chip qualification sample (QS). Probably, the AMD compensates for low clock frequencies with a proportional increase in operations per clock (IPC), an increase in volume L3 or a relatively low thermal capacity of the CPU.
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