Heterogeneous architectures with processors, GPUs and memory on a common substrate have become the main focus for the development of supercomputations and AI accelerators. At the level of microcircuits, this is manifested in a multi-chip layout both in one plane and in three dimensions. Thus, the coordinated work of all the constituent parts of the “superchip” comes to the fore, which requires in-depth architectural developments and encourages them to be protected with patents.
But before continuing, let us return four and a half years ago. In August 2015, it became known that AMD was developing a powerful APU called the Exascale Heterogeneous Processor (EHP). Everything that was known about the project, we reported in the news for August 3, 2015. Nothing more was heard of EHP until this week. In brief, EHP was a hybrid 32-core solution with an estimated 3072 stream processors and HBM2 on-board memory of at least 32 GB.
In subsequent years, Zen architecture and newer versions made it possible for 32- and even 64-core processors in a multi-chip layout. However, the company did not introduce APUs like the EHP project. Interestingly, in March this year, AMD Technical Director Mark Papermaster admitted that the company is developing multi-chip packaging projects with crystals (chipsets) in the same plane on a single substrate and in a 3D spatial configuration (X3D).
The spatial layout will allow the GPU and CPU to be located one above the other, while in the picture with the EHP project, the computing cores are huddled on the periphery of the GPU. However, the fashionable approach with CPU and GPU chipsets will allow the crystals to be placed in the same plane. Modern interchip (intercrystal) AMD buses allow this. This makes it easier to cool the crystals, although you have to sacrifice small delays.
But this is all a saying. The tale is that one of the enthusiasts discovered a package of new AMD patents, in which the company talks about developed heterogeneous architectures and as yet not implemented technologies for GPUs. For example, one of the patents refers to the dynamic memory management of the GPU. This makes special sense if the onboard and shared memory for the GPU and CPU is HBM memory.
From this, our colleagues at WCCFTech concluded that AMD continues to secretly work on the Exascale Heterogeneous Processor project. In our opinion, they give out wishful thinking. But this does not mean at all that AMD is not working on a heterogeneous architecture for supercomputations, when many computing and graphic cores will work in concert as a conditionally single processor. As for the abbreviation EHP, then Intel projects, ARM projects, and many others can rightfully try it on themselves. That is the tendency.
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