Semidynamics Secures Strategic Investment from SK hynix to Transform AI Inference
The economics of artificial intelligence are shifting. While raw compute power once dominated the conversation, the industry is hitting a “memory wall” where data movement bottlenecks stifle performance. In a move to solve this critical challenge, Barcelona-based Semidynamics announced on April 8, 2026, that it has secured a strategic investment from SK hynix, a global leader in memory manufacturing.
This partnership signals a pivot toward memory-centric AI infrastructure. By focusing on how data is stored and accessed rather than just how prompt it is processed, Semidynamics aims to drastically reduce the cost per token—the primary metric for the viability of large-scale AI deployments.
- Strategic Backing: SK hynix has invested in Semidynamics to advance memory-centric AI inference chips.
- Architectural Shift: The company uses a proprietary RISC-V implementation designed from the ground up to overcome memory bottlenecks.
- Hardware Milestones: Semidynamics achieved a 3nm chip tape-out with TSMC in December 2025.
- Full-Stack Approach: The company is developing a vertically integrated platform including chips, boards, and rack-level systems.
Solving the Memory Wall in AI Inference
As large language models (LLMs) scale and agentic, multi-turn workloads develop into common, they require persistent context across long sessions. This puts immense pressure on memory capacity and data movement. Traditional HBM-based (High Bandwidth Memory) systems often struggle to keep up, limiting the number of users a single rack can support.
Semidynamics tackles this by delivering significantly more memory capacity than conventional systems. This allows for:
- Larger Models: Running more complex AI models without performance degradation.
- Larger KV-Caches: Improving the efficiency of how models remember previous parts of a conversation.
- Larger Contexts: Enabling the processing of more data within a single inference session.
These improvements lead directly to a lower cost per token, making high-performance AI more accessible and sustainable for data centers.
The Technology: RISC-V and Gazzillion®
Unlike many companies that attempt to retrofit existing compute architectures for AI, Semidynamics built its platform from first principles. The company uses an open RISC-V architecture, modified specifically to address the memory wall.
At the heart of this system is the proprietary Gazzillion® memory subsystem. Supported by a growing patent portfolio, this technology is engineered to reduce the bottlenecks that typically constrain AI infrastructure, ensuring that the processor isn’t left idling while waiting for data to arrive from memory.
From Silicon to Racks: A Full-Stack Strategy
Semidynamics isn’t just designing a chip; it’s building a complete AI ecosystem. In February 2026, the company unveiled its roadmap for full-stack AI infrastructure, which encompasses:
- Inference Silicon: High-performance chips designed for memory efficiency.
- Custom Boards: Optimized circuitry to support the silicon’s data flow.
- Rack-Level Systems: Vertically integrated hardware for data-center-scale deployments.
A major technical validation of this strategy occurred in December 2025, when Semidynamics achieved “tape-out” at the 3nm node with TSMC. As Roger Espasa, CEO of Semidynamics, noted, this milestone is a vital step toward delivering production-grade silicon and rack-scale systems designed in Europe.
Comparison: Traditional vs. Memory-Centric Inference
| Feature | Conventional HBM Systems | Semidynamics Approach |
|---|---|---|
| Primary Focus | Raw Compute Power | Memory Architecture |
| Architecture | Compute-centric (Retrofitted) | RISC-V (Built for Memory) |
| Main Constraint | Data movement bottlenecks | Optimized via Gazzillion® subsystem |
Frequently Asked Questions
What is the “Memory Wall” in AI?
The memory wall refers to the growing gap between how fast a processor can compute data and how fast that data can be moved from memory to the processor. In AI inference, this often means the processor wastes time waiting for data, which increases costs and slows down performance.
Why is the 3nm tape-out significant?
Tape-out is the final stage of the design cycle before a chip is sent for manufacturing. Achieving this at the 3nm node—one of the most advanced processes available via TSMC—proves that Semidynamics’ complex architectural designs are physically viable and ready for production.
How does this investment affect the AI market?
By partnering with SK hynix, Semidynamics combines cutting-edge memory manufacturing with innovative architecture. This could shift the market focus from simply adding more GPUs to creating more efficient, memory-optimized systems that lower the total cost of ownership for AI data centers.
Looking Ahead
The investment from SK hynix validates a critical thesis: the future of AI isn’t just about who has the fastest chips, but who can move data most efficiently. As Semidynamics moves from its 3nm tape-out toward deploying full-stack rack systems, the industry will be watching to see if this memory-centric approach can truly break the bottlenecks of modern AI inference.
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