AMD Launches Epyc 6 Venice Server CPUs
Advanced Micro Devices Inc. debuted its sixth-generation server processor series, code-named Venice, featuring 10 central processing units split into two distinct capability groups, SiliconANGLE reported.
The lineup consists of chips designed to support artificial intelligence agents by powering their underlying toolsets and machine learning clusters.
The processor family relies on the new Zen 6 core architecture built on Taiwan Semiconductor Manufacturing Co.’s two-nanometer manufacturing node. The architecture delivers an average 27% increase in instructions per clock compared with Zen 5 in selected server workloads. The design includes both standard Zen 6 cores optimized for clock speed and scaled-down Zen 6c cores engineered for high core counts.
Epyc 6 Processors Feature High-Frequency and High-Density Configurations
The Epyc 6 series divides its processors into high-frequency models and high-density chips. The two highest-frequency processors feature 96 cores, a 384-megabyte cache, a base speed of 4.05 gigahertz, and a boost clock reaching 5.3 gigahertz under demanding conditions, according to SiliconANGLE. The architecture increases the standard Zen 6 CCD core count from eight to 12 while expanding the shared L3 cache to 48 megabytes.
The densest processors in the lineup house 256 cores with a base speed of 2.55 gigahertz. Because each core supports two threads, these high-density models handle up to 512 threads simultaneously. Zen 6c doubles its cores per CCD from 16 to 32 and expands L3 cache fourfold to 128 megabytes, giving each core 4 megabytes of L3 cache alongside a private 1 megabyte L2 cache.
AI Workload Optimizations
AMD designed the Venice series to run artificial intelligence agents, which utilize graphics cards for neural networks and CPUs for application tools. SiliconANGLE reported that Epyc 6 processors support up to 3.3 more agents per watt than Nvidia Corp.’s Vera CPU while outperforming comparable Intel Corp. silicon.
The underlying architecture incorporates specific hardware features for AI processing. Zen 6 adds full AVX-512 FP16 support, new Bit Matrix Multiply instructions, and four VNNI-INT8 pipelines. These additions allow systems to compress processed information, execute multiple AI calculations in a single operation, and lower overall hardware footprints.
Reducing Software Expenses Through Core Count Optimization
Deploying AI tools on CPUs with a relatively small core count can reduce software expenses in some cases. Many enterprise applications, including databases, are billed according to the number of cores on which they run. Deploying a database on one high-frequency core is cheaper than using two slower ones that together provide the same amount of processing power.
Dan McNamara, senior vice president and general manager of AMD’s Compute and Enterprise AI unit, stated that AI is expanding the CPU's role across every layer of the data center. With 6th Gen AMD EPYC, customers can standardize on the proven x86 foundation while choosing a workload-optimized solution to run more agents,
McNamara said.
Data Center Suppliers Ship Servers with Epyc 6 Processors
Major data center suppliers have already begun shipping servers equipped with Epyc 6 processors. SiliconANGLE reported that the new chips also power a pair of Microsoft Azure instances optimized for AI inference workloads and chip design software. The platform supports PCIe 6.0 and DDR5 MRDIMM memory at up to 12,800 MT/s.
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