CEA-List and CEA-Leti Unveil First Dynamically Routed Electro-Optical Router for Photonic Interposers

Researchers from CEA-List and CEA-Leti have announced a breakthrough in optical networking with the demonstration of the first electro-optical router featuring dynamic, frame-level optical routing integrated with CMOS control logic. This innovation, presented at the International Solid-State Circuits Conference (ISSCC) on February 18, 2026, marks a significant step towards practical optical networking within advanced chiplet-based packages. Semiconductor Digest and EEJournal reported on the development.

Addressing Limitations of Current Optical Interconnects

Today’s optical interconnects are primarily limited to static, point-to-point links, often requiring initialization and training times ranging from microseconds to milliseconds. While suitable for board-level or rack-scale communication, these latencies hinder the use of optical links as a true networking fabric inside multi-die packages. The newly developed router addresses this limitation by integrating optical switching, routing control, serializer/deserializer (SerDes), and clocking logic directly with silicon photonics.

Key Features and Performance

The electro-optical router, implemented in 28 nm CMOS on a photonic interposer, is capable of establishing optical paths in just 18 nanoseconds. It dynamically selects between one and six wavelengths per link, achieving an energy efficiency of 3.19 pJ/bit with an active area of only 0.007 mm² per link. The research was detailed in the paper, “A 3.19pJ/bit Electro-Optical Router with 18ns Setup Frame-Level Routing and 1-6 Wavelength Flexible Link Capacity for Photonic Interposers.”

Dynamic Routing and Flexibility

This router supports frame-level routing, enabling optical paths to be established and torn down on demand. Its ability to adjust link capacity dynamically by selecting between one and six wavelengths allows for efficient use of optical bandwidth while maintaining ultra-low latency. This flexibility is crucial for applications requiring adaptable data transfer rates.

Implications for High-Performance Computing and AI

According to Yvain Thonnart, lead author from CEA-List, this technology is essential as chiplet systems grow in scale and complexity. CEA-List’s LinkedIn post highlights that the dynamic, ultra-low-latency optical networking opens new possibilities for high-performance computing (HPC), AI accelerators, and data-intensive systems. The router allows architects to treat memory and compute resources across the interposer as part of a unified fabric without sacrificing latency or energy efficiency, moving beyond the need to locate all data near compute cores to minimize electrical routing costs.

ISSCC 2025 Presentation

CEA-Leti likewise presented related research at the International Solid-State Circuits Conference (ISSCC) in 2025.