Panmnesia to Mass-Produce PCIe 6.4-CXL 3.2 Fusion Switch

by Anika Shah - Technology
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Panmnesia to Mass-Produce PCIe 6.4-CXL 3.2 Fusion Fabric Switch for AI Infrastructure

As large-scale AI applications like ChatGPT become pervasive, the bottleneck for system performance has shifted from raw compute power to inter-device communication. To solve this, South Korean fabless company Panmnesia has announced the mass production of its PCIe 6.4-CXL 3.2 fusion fabric switch. This silicon represents a significant leap in how data centers interconnect memory, compute, and accelerator devices.

Breaking the Bottleneck: What is PanSwitch?

The PanSwitch (model H1SW06245ACFAA) is the world’s first hybrid switch to fully support both PCIe 6.4 and CXL 3.2 specifications on a single die. Unlike traditional network-based approaches, such as Ethernet—which often introduce long latencies due to software stack overhead—PanSwitch allows a vast number of devices to interconnect directly via CXL.

By serving as an intermediary bridge, the switch connects diverse system resources, including PCIe-based GPUs, CXL CPUs, CXL memory expanders, and CXL-based AI accelerators. This creates a unified, composable fabric designed specifically for the rigorous demands of AI data centers and high-performance computing (HPC) environments.

The Innovation of Port-Based Routing (PBR)

A standout feature of the PanSwitch is its full implementation of Port-Based Routing (PBR). To understand why this matters, one must gaze at traditional hierarchy-based routing, which limits devices to tree topologies. PBR removes these restrictions, directing signals based on ports assigned to each device.

The Innovation of Port-Based Routing (PBR)
Panmnesia Based Routing Port

This capability allows engineers to connect devices in any desired topology, providing unprecedented flexibility in system architecture. When combined with a high fan-out architecture, PanSwitch enables the interconnection of thousands of devices into a single, manageable fabric.

Technical Specifications and Performance

Panmnesia has engineered the PanSwitch to minimize performance overhead while maximizing bandwidth. The switch achieves double-digit nanosecond latency (sub-100ns), which is critical for memory expansion in AI workloads.

Specification Detail
Protocols PCIe 6.4, CXL 3.2 (Backward compatible)
Number of Lanes 256 lanes (World’s highest fanout)
Data Rate 64 GT/s
Bifurcation Support x4, x8, x16
Supported Subprotocols CXL.io, CXL.mem
Latency Double-digit nanoseconds

Enabling Composable Architecture at Rack Scale

The fusion fabric switch is the cornerstone of a “composable architecture.” In this model, system resources are pooled and managed independently, then flexibly allocated based on the specific demands of an application.

Make AI Clusters Act Like One Large Unified Accelerator – PCIe 6.4/CXL 3.2 Switch (CES2026 Trailer)

By implementing this at rack scale, Panmnesia helps AI data centers minimize resource waste. Instead of having stranded memory or underused GPUs, the fabric allows for real-time load balancing and automated resource optimization, ensuring that the right amount of compute and memory is delivered to the right workload at the right time.

Availability and Roadmap

Panmnesia, led by CEO Myoungsoo Jung, first unveiled a sample of the silicon in October 2025. The company further showcased the PanSwitch and its accompanying PANRDK™ development board—designed for pilot system deployment and validation—at CES 2026 in Las Vegas.

Availability and Roadmap
Panmnesia Based Routing Port

The company has confirmed that it will begin mass-producing the PCIe 6.4-CXL 3.2 fusion fabric switch in the second half of 2026. Currently, the silicon is available for early access partners who can request samples and pilot systems to begin integrating the technology into their infrastructure.

Key Takeaways

  • First of its Kind: PanSwitch is the first switch to fully implement CXL 3.2, including Port-Based Routing.
  • Massive Scalability: Features a 256-lane high fan-out architecture to connect thousands of devices.
  • Ultra-Low Latency: Delivers double-digit nanosecond latency to reduce AI infrastructure costs, and overhead.
  • Resource Efficiency: Enables rack-scale composable architecture to reduce resource waste in HPC and AI environments.

Frequently Asked Questions

What is the difference between PBR and hierarchy-based routing?

Hierarchy-based routing is limited to tree topologies, meaning devices must follow a strict parent-child structure. Port-Based Routing (PBR) allows devices to be connected in any topology, offering significantly more flexibility in how a system is built.

Which devices can be connected using PanSwitch?

The switch supports a wide array of modern data center hardware, including PCIe-based GPUs, PCIe switches, CXL CPUs, CXL memory expanders, and CXL-based AI accelerators.

When will the PanSwitch be available for mass market use?

Panmnesia plans to start mass production of the fusion fabric switch in the second half of 2026, though early access partners can currently request samples.

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