Quantum Leap in Chip Design: Supercomputer Simulation Accelerates Next-Gen Hardware

Researchers at Berkeley Lab have achieved a significant milestone in quantum computing, successfully simulating a complete quantum chip with unprecedented detail using the Perlmutter supercomputer. This breakthrough, leveraging nearly all 7,168 NVIDIA GPUs, promises to accelerate the development of more powerful and reliable quantum hardware by allowing scientists to predict chip behavior before fabrication.

The Challenge of Quantum Chip Design

Designing quantum chips is a complex undertaking, requiring expertise in both traditional microwave engineering and advanced low-temperature physics. Traditional methods often treat chips as “black boxes” due to computational limitations, hindering the ability to optimize performance and identify potential issues. Modeling quantum chips allows researchers to understand their function and performance before they’re fabricated, ensuring they function as intended and spotting any problems that might come up.

ARTEMIS and the Power of Exascale Computing

To overcome these challenges, researchers Zhi Jackie Yao and Andy Nonaka of the Applied Mathematics and Computational Research (AMCR) Division at Berkeley Lab developed an exascale modeling tool called ARTEMIS. ARTEMIS, originally developed as part of the Department of Energy’s Exascale Computing Project, is a classical electromagnetic modeling tool ideally suited for simulating the intricate structures of quantum chips.

A Record-Breaking Simulation

The team used ARTEMIS to model and optimize a chip designed in collaboration with Irfan Siddiqi’s Quantum Nanoelectronics Laboratory at the University of California, Berkeley, and Berkeley Lab’s Advanced Quantum Testbed (AQT). The simulation involved a multi-layered chip measuring just 10 millimeters square and 0.3 millimeters thick, with etchings as small as one micron. This required nearly all of Perlmutter’s 7,168 NVIDIA GPUs operating for 24 hours.

“I’m not aware of anybody who’s ever done physical modeling of microelectronic circuits at full Perlmutter system scale. We were using nearly 7,000 GPUs,” said Nonaka. The researchers discretized the chip into 11 billion grid cells and ran over a million time steps in seven hours, evaluating three circuit configurations in a single day.

Beyond Simplification: Full-Wave Physical Modeling

Unlike many simulations that simplify chip components, this approach focused on full-wave physical-level modeling. According to Yao, this means considering the materials used, the chip layout, the wiring, and the size and shape of resonators. The simulation also recreates how the chip would behave during real experiments, including qubit interactions.

Capturing Real-Time Quantum Behavior with Maxwell’s Equations

The simulation utilizes Maxwell’s equation in the time domain, allowing researchers to account for nonlinear effects and track how signals evolve. This combination of detailed physical modeling and time-based simulation is a key aspect of the project’s uniqueness.

Future Directions and Collaboration

The team plans to expand their simulations to gain a more precise understanding of the chip’s performance within larger systems. They aim to quantitatively simulate the spectral behavior of the system and benchmark it against frequency-domain simulations. The model will be tested against experimental results once the chip is fabricated.

This achievement was a collaborative effort involving researchers from Berkeley Lab, the University of California, Berkeley, and NERSC, which provided both computing power and technical expertise. According to Bert de Jong, director of the Quantum Systems Accelerator (QSA), this work is a critical step toward accelerating the design and development of quantum hardware.

Yao will present this research in a technical demonstration at the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC25).