Semiconductor Scaling: Comparing SMIC’s N+3 Process and Intel’s 18A Node

Recent analysis indicates that Semiconductor Manufacturing International Corporation’s (SMIC) N+3 node and Intel’s 18A process represent distinct approaches to sub-7nm logic scaling. While SMIC’s N+3 process focuses on maximizing density within the limitations of deep ultraviolet (DUV) lithography, Intel’s 18A utilizes gate-all-around (GAA) RibbonFET architecture and backside power delivery to target performance parity with leading-edge nodes from TSMC. Experts note that despite potential similarities in metal pitch metrics, the underlying transistor technologies and manufacturing constraints create significant differences in real-world performance and power efficiency.

How do SMIC N+3 and Intel 18A compare technically?

The primary technical differentiator between the two nodes is the transistor architecture. According to Intel’s official disclosures, the 18A process features RibbonFET, the company’s implementation of gate-all-around (GAA) transistors. This design allows for better electrostatic control of the channel compared to the FinFET structures used in SMIC’s N+3 node. While SMIC has successfully pushed DUV-based multi-patterning to achieve high-density logic, it remains constrained by the lack of extreme ultraviolet (EUV) lithography equipment due to international export controls. Intel, conversely, integrates EUV lithography into its 18A workflow, which simplifies the manufacturing process and reduces the reliance on complex multi-patterning techniques that can introduce yield-degrading defects.

What is the significance of metal pitch in process scaling?

Metal pitch—the distance between the center of one metal line and the center of the next—is a key indicator of how tightly a chipmaker can pack transistors. Industry analysts at SemiAnalysis have highlighted that while SMIC’s N+3 metal pitch may approach dimensions seen in more advanced nodes, pitch alone does not dictate chip performance. A smaller metal pitch theoretically allows for higher density, but it also increases resistance and capacitance, which can hinder signal speed. Intel’s 18A addresses these parasitic effects through its PowerVia technology, a backside power delivery network that separates power and signal routing. This innovation allows Intel to maintain performance gains even if the raw metal pitch isn’t significantly smaller than that of competitors.

Why does the manufacturing method matter for yield?

The reliance on DUV versus EUV lithography is the most critical factor in the long-term viability of these nodes. SMIC’s N+3 process relies on aggressive multi-patterning, where a single layer of the circuit is created through several exposure steps. According to reports on export controls, this approach is inherently more expensive and prone to lower yields as complexity increases. Intel’s 18A process leverages EUV, which reduces the number of masks required for complex designs. This not only lowers the risk of manufacturing errors but also improves the time-to-market for high-performance computing and AI-focused silicon, which require large die sizes that are difficult to produce reliably with high-count multi-patterning.

Comparison Summary

What happens next in the foundry race?

The industry is moving toward 2nm and beyond, where gate-all-around architecture will become the standard for all major foundries. For SMIC, the challenge remains the transition to EUV lithography, without which scaling gains will likely plateau. Intel is currently working to scale 18A for high-volume manufacturing, with several third-party clients already committed to the node. As foundries compete for AI chip orders, the focus is shifting away from simple pitch metrics toward total energy efficiency and the ability to produce large, complex processors at scale.