Cisco Seeks ASIC Engineering Technical Leader in San Jose, Focusing on Design-for-Test
Cisco is hiring an ASIC Engineering Technical Leader specializing in Design-for-Test (DFT) to join its Silicon One development organization in San Jose, California. This role focuses on driving DFT requirements early in the chip design cycle, collaborating with both front-conclude RTL and back-end physical design teams.
Silicon One and Cisco’s Hardware Group
The position is within Cisco’s Common Hardware Group (CHG), responsible for the silicon, optics, and hardware platforms powering Cisco’s switching, routing, and wireless products. Cisco Silicon One is a unifying silicon architecture designed for a wide range of networking applications, from Top of Rack (TOR) switches to web-scale data centers and service provider networks .
Role and Responsibilities
As an ASIC Technical Lead, the individual will play a key role in shaping Cisco’s next-generation ASIC solutions. The role requires a primary focus on Design-for-Test (DFT) methodologies. The position involves working within a startup-like atmosphere, while benefiting from the stability of a large corporate environment. All hardware and software development fields are hosted within a single design center .
Key Takeaways
- Location: San Jose, California
- Focus: Design-for-Test (DFT)
- Organization: Cisco Silicon One development within the Common Hardware Group
- Collaboration: Requires working with RTL and physical design teams
About Cisco Silicon One
Cisco Silicon One is central to Cisco’s ASIC design efforts and is driving the development of next-generation network devices, particularly those supporting Artificial Intelligence/Machine Learning (AI/ML) applications .
Please Note: As of April 3, 2026, Cisco is not accepting new applications for this role. Interested candidates are encouraged to check back for updates or explore other opportunities with the company .