Back-Finish Automation Evolves to Tackle Semiconductor Packaging Complexity

As semiconductor packaging advances with technologies like chiplets, 3D stacks, and fine-pitch interconnects, the need for sophisticated back-end automation is becoming increasingly critical. Experts are focusing on challenges related to thermal management, data integration, handling larger and thinner wafers, and leveraging artificial intelligence (AI) to improve yield and efficiency.

Thermal Management and Device Handling

The increasing power requirements of modern devices—reaching up to 3,000 watts—demand improved thermal performance during testing. According to Michael Lowman, senior product marketing manager for Data Analytics at Cohu, ensuring devices aren’t damaged during testing requires in-line inspection of handling equipment, allowing for real-time reaction to potential issues. Beyond thermal concerns, the physical size of devices is also presenting challenges. Larger and taller devices necessitate more complex handling mechanisms, sometimes requiring two heads instead of one for pickup.

The Data Integration Challenge

A significant hurdle in back-end automation is the integration of data from various inspection and metrology tools. Aftkhar Aslam, CEO at yieldWerx, highlights that tools like optical inspection, X-ray, and acoustic systems generate data in different formats and coordinate systems. Customers are seeking a unified platform to consolidate this data, trace root causes of defects, and implement corrective actions across the entire manufacturing process—from design to final assembly. The ability to sequence data by timeframe is also crucial for identifying the origin of problems.

Evolving Form Factors and Inspection Requirements

Changes in packaging form factors are driving new requirements for inspection and metrology equipment. Woo Young Han, product marketing director at Onto Innovation, notes the trend toward triple-bonded wafers exceeding two millimeters in thickness, introducing significant stress and warpage. The demand for sub-micron inspection on warped surfaces with high contour variation presents a considerable challenge. Wafer-level molding, common in chiplet packaging and HBM, introduces new defect types, particularly at the edges and backside, impacting yield.

Handling Large and Thin Wafers

ASE is experiencing similar challenges with wafer size and warpage. Lihong Cao, senior director of engineering and technical marketing for ASE, points to increasing wafer sizes—moving towards 100x100mm, 150mm, and even 170mm—and greater warpage, now exceeding three millimeters. Thin wafer handling, with wafers as thin as 50-100 microns, also presents difficulties, requiring automation to control particle contamination and meet the demands of fine line spacing (two microns or less).

The Role of AI and Closed-Loop Systems

To address these complexities, companies are exploring the utilize of AI to consolidate data and streamline processes. Lowman suggests a practical approach: starting with a closed-loop system focused on a specific area, such as test and finishing, to learn and establish standards before expanding to more heterogeneous data environments. Aslam emphasizes the potential of AI-assisted correlation engines to pinpoint root causes of defects and enable feed-forward control, adjusting test limits based on manufacturing data. Han notes increasing requests for data formats compatible with machine learning and AI-based analysis, such as gRPC. Cao highlights the use of AI for in-line data analysis and yield learning within ASE’s internal closed-loop system.

Standardization and Data Communication

A lack of standardization in data formats remains a key obstacle. Cao notes that ASE receives data in varying formats from different customers and foundries, requiring internal systems to manage these differences. The industry is moving towards more machine learning-friendly data transfer systems to facilitate AI-driven analysis.