## the NanoIC pilot line has the ambition to become the world’s specialised R&D pilot line on beyond semiconductor technology.
With the aim to support the European Chips Act’s vision to reinforce Europe’s leadership in the global semiconductor ecosystem and drive innovation in critical markets like computing,dialog,mobility,energy,and health. Serving as a vital bridge between cutting-edge research and commercial applications, the NanoIC pilot line is central to consolidating Europe’s position at the forefront of semiconductor innovation and competitiveness.
To bridge the gap between research innovation and commercialisation in the semiconductor industry, a robust lab-to-fab conduit is essential. The NanoIC pilot line fosters innovation in computing system architectures by maturing specific semiconductor technologies. The goal is to enable European companies to further led in semiconductor innovation.
Specifically, the NanoIC pilot line provides a beyond 2nm system-on-chip (SoC) pilot line for the growth and maturation of selected advanced logic, memory, and interconnect technologies. The project focuses on large-scale capacity building,especially in imec’s cleanroom in Leuven (Belgium),joint R&D,maturation of advanced technologies towards prototyping,and innovation support,providing the entire semiconductor ecosystem access to these advanced technologies. Participants can engage with the NanoIC pilot line in ways that best suit their specific needs and innovation goals, regardless of their role in the value chain.This will allow early insights into the emerging fields and support Europe to maintain its competitiveness across the entire semiconductor value chain: from materials, equipment, processes and devices to designs and systems.### NanoIC consortium
The NanoIC pilot line project consortium is led by imec, alongside CEA-Leti in France, Fraunhofer-Gesellschaft (FhG) in Germany, VTT Technical Research center in Finland, Tyndall National Institute in ireland, and the Center for Surface Science and Nanotechnology of the University Politehnica of Bucharest in Romania.It is supported by the Flemish Government, other participating states, and the Chips Joint Undertaking. All partners together strive to make the implementation of the pilot line a success.
### Building blocks of future compute systems
Nanosheet class of logic devices are anticipated to drive scaling and performance through three more generations (N2, A14, A10). Complementary field effect transistor (CFET) architectures are currently projected to be introduced around 2031 at the A7 node, representing a major inflection point in CMOS device design. progression in this field demands extensive research into new materials, process modules, equipment, and advanced patterning capabilities, for which high numerical aperture extreme ultraviolet (high NA EUV) lithography comes into play.
Memory innovations are focusing on novel magnetic memories, more specifically spin orbit torque-magnetic random access memory (SOT-MRAM) and embedded Dynamic Random Access Memory (eDRAM). For the latter, an option 2T0C configuration is developed, including the exploration of semiconductors with wide bandgaps, such as semiconducting oxides like indium-gallium-zinc-oxide or 2D transition metal dichalcogenides, which are considered promising alternative channel materials. In parallel, developing a 3D memory platform to explore future novel memory options – to augment SRAM and DRAM – is essential to address memory capacity and memory bandwidth challenges from new workloads.
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NanoIC Pilot Line Opens Doors to Next-Gen Chip Design
Table of Contents
Imec has launched a new pilot line focused on NanoIC (Nano-Integrated Circuits), offering a unique platform for exploring and validating next-generation chip designs. This initiative aims to accelerate innovation in the semiconductor industry by providing access to advanced process technologies and design tools.
What is nanoic?
NanoIC represents a shift towards more heterogeneous and specialized chip architectures.Instead of relying solely on conventional CMOS scaling, NanoIC integrates various functional blocks – like sensors, power management, and RF components – directly onto the chip alongside the core logic. This allows for optimized performance, reduced power consumption, and new functionalities.
Key Features of the Imec pilot Line
- Advanced Process Technologies: The pilot line supports a range of cutting-edge technologies,including 3D integration,advanced packaging,and novel materials.
- Pathfinding PDK: A pathfinding Process Development Kit (PDK) is available, enabling early design exploration for start-ups, universities, and design companies.
- Collaboration Opportunities: Imec actively encourages collaboration with equipment and materials suppliers to test and refine new tools and processes.
- Baseline Exploration: Integrated device manufacturers and foundries can utilize established baselines to explore new modules and performance enhancements.
Who Benefits from the NanoIC Pilot Line?
The NanoIC pilot line offers benefits to a wide range of stakeholders:
- Integrated Device Manufacturers (IDMs) & Foundries: Can explore new modules and performance enhancements.
- Equipment & Materials Suppliers: Gain a platform to test and refine new tools and processes.
- Start-ups, Universities & Design Companies: Access a pathfinding PDK for early design exploration.
FAQ
Q: What types of NanoIC designs can be explored on the pilot line?
A: The pilot line supports a broad range of NanoIC designs, including those incorporating sensors, power management circuits, RF components, and memory.
Q: How can companies